A method of compressing/extending compressed data using a run length coding and a variable length coding is used in JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group), which are general technologies for compressing image data. Along with the spread of a digital camera and a digital video camera and the advancement of the communication technology, the method has been made widely available as a technology capable of transferring data with a small volume of information.
A typical example of an image compression device is shown in FIG. 36. Below is given a description of the device referring to FIG. 36
Image data divided into blocks each comprising 8×8 pixels beforehand and serially inputted is frequency-converted in a DCT (Discrete Cosine Transform) unit 101 for executing a discrete cosine conversion so as to generate a DCT coefficient. Inmost of natural images, colors smoothly changes. As a result of executing the frequency-conversion, the DCT coefficients having larger values gather in a low-frequency region m, while the DCT coefficients having smaller values are distributed in a high-frequency region n as shown in FIG. 37. A coefficient in an upper-left corner, in particular, is referred to as a DC component having no frequency component, and any other coefficient is referred to as an AC component.
In a quantization unit 102, the DCT coefficient is divided by a preset quantization value so as to generate a quantization coefficient. As a result of the processing, the coefficients of “0” can be aggregated in the high-frequency region which does not affect an image quality.
In a variable length coding unit 103, “RUN” representing the number of “0” and “LEVEL” representing the magnitude of the coefficient value are combined in the order of a zigzag scan as shown in FIG. 38 so as to generate run length data. In compliance with the appearance ratio of the foregoing combinations, code words having different lengths are allocated so as to reduce a data capacity.
An image extension device for decoding the variable length code data coded in the foregoing manner comprises a variable length decoding unit 104, an inverse quantization unit 105 and an inverse DCT unit 106, which correspond to the constitution of the image compression device, as shown in FIG. 39.
In the variable length decoding unit 104, the data is decoded in the state in which the “RUN” representing the number of “0” and the “LEVEL” representing the magnitude of the coefficient value are combined, and the “0” coefficients as many as the magnitude of the “RUN” are generated and combined with the coefficients represented by the “LEVEL”. This operation is repeated until the coefficients corresponding to 8×8 pixels are generated.
The generated coefficients corresponding to 8×8 pixels are multiplied by a preset quantization value in the inverse quantization unit 105 so as to obtain an inverse-quantization DCT coefficient. Further, the coefficients are subjected to a frequency region—spatial region conversion in the inverse DCT unit 106, and the image data is thereby decoded.
A conventional constitution of the variable length decoding unit 104 is described referring to FIG. 40.
The variable length code data inputted from an input unit 107 is decoded in a variable length decoding unit 108 in the state in which the “RUN” representing the number of “0” and the “LEVEL” representing the magnitude of the coefficient value are combined. A write control unit 109 supplies a selection signal to a selector 110 so that “0” as many as the number of the decoded “RUN” are written in a data buffer 112. After “0” corresponding to the number of the decoded “RUN” are written, the coefficients represented by the “LEVEL” are written in the data buffer 112. This operation is repeated until the coefficients as many as the 8×8 pixels are generated, and then, the data is serially read from the data buffer 112 by a read control unit 111 in the order of the zigzag scan (FIG. 38) and outputted from an output unit 113 to the inverse quantization unit 105.
However, in the conventional constitution, during a period when the “0” coefficients as many as the number of the decoded “RUN” are consecutively written, the processing of the variable length decoding unit 108 cannot be executed. The disadvantage resulted in the generation of an idle period, which was unfavorably an impediment in achieving a higher-speed operation.
As a solution of the aforementioned problem was proposed a run length code decoding circuit disclosed in No. 08-167856 of the Publication of the Unexamined Japanese Patent Applications (p. 4–7, FIG. 7). Below is described an example of the run length code decoding circuit referring to FIG. 41.
All of data words stored in a first data buffer 116 and a second data buffer 117 are initialized to “0” beforehand. The variable length code data inputted from an input unit 114 is decoded in a variable length decoding unit 115 in the state in which the “RUN” representing the number of “0” and the “LEVEL” representing the magnitude of the coefficient value are combined. The “LEVEL” data is supplied to selecting units 122 and 123, while the decoded “RUN” data is supplied to an address adder 118 so that only values of the “RUN” are linearly added, and then, a result of the addition is outputted to a write control unit 119. The outputted data is converted into zigzag scan addresses in the write control unit 119, and a result of the conversion is outputted to selecting units 124 and 125. The address adder 118 serves to supply an “H” level to the selecting units 122 and 124 or the selecting units 123 and 125 as a selection signal, while supplying the other with an “L” level, and invert a logic “LEVEL” of the selection signal before the processing corresponding to 8×8 pixels is completed.
A read control unit 120 outputs an read address to the data buffer 117 when the address adder 118 supplies the selecting units 122 and 124 with the “H” level, while outputting the read address to the data buffer 116 when the address adder 118 supplies the selecting units 123 and 125 with the “H” level. Output data is outputted from one of the data buffers 116 and 117 via an output unit 126 or 127 in accordance with the read address from the read control unit 120.
When the read address is outputted from the read control unit 120 to the data buffer 116 or 117, an initializing unit 121 outputs the same address by a slightly shifted timing as an initialization address to the selecting unit 124 or 125.
The selecting units 122 and 123 output the “LEVEL” data from the variable length decoding unit 115 to the relevant data buffers 116 and 117 when the selection signal from the address adder 118 is the “H” level, while outputting “0” thereto when the selection signal is the “L” level.
The selecting units 124 and 125 output the zigzag scan addresses from the write control unit 119 when the selection signal form the address adder 118 is the “H” level, while outputting the initialization address from the initializing unit 121 when the selection signal is the “L” level.
The addresses from the address adder 118 and the read control unit 120 are initialized to an initial value every time when the processing corresponding to 8×8 pixels is completed.
According to the decoding circuit shown in FIG. 41, only the “LEVEL” data overwrites “0” at the position identified in the zigzag scan addresses is based on the decoded run length code after all of the data stored in the first data buffer 116 is initialized to “0”. Thus, one block stored in the second data buffer 117 is read and initialized during the period when only the non-“0” components of the 8×8 pixels constituting one block are written in the first data buffer 116.
According to the conventional technology, when the data stored in the data buffer is initialized to “0” in advance, and only the “LEVEL” data is written at the corresponding position in the data buffer based on the run length code, the processing required for one block can be reduced in accordance with the number of the non-“0” components of the 8×8 pixels constituting one block.
However, it becomes necessary to initialize the data buffer in the foregoing conventional constitution. Further, the idle time generated between the decoding process and the read operation and the number of accesses with respect to the data buffer could not be disadvantageously reduced because all of the data was necessarily read from the data buffer.